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This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a device's latch-up capability so that both the user and supplier understand a device's latch-up capabilities. It is applicable to NMOS, CMOS, Bipolar, and all variations and combinations of these technologies. Latch-up is an extremely important factor in determining product reliability. This document contains the corrected figure 4 to include T6 on page 12, this change was made in January 1998.
 

Document History

  1. JEDEC JESD78E


    IC LATCH-UP TEST

    • Most Recent
  2. JEDEC JESD78D


    IC LATCH-UP TEST

    • Historical Version
  3. JEDEC JESD 78C


    IC LATCH-UP TEST

    • Historical Version
  4. JEDEC JESD 78B

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    IC LATCH-UP TEST

    • Historical Version