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JEDEC JESD78E

IC LATCH-UP TEST

standard by JEDEC Solid State Technology Association , 04/01/2016

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This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.
 

Product Details

Published:
04/01/2016
Number of Pages:
32
File Size:
1 file , 750 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus
 

Document History

  1. JEDEC JESD78F.02


    IC LATCH-UP TEST

    • Most Recent

  2. JEDEC JESD78F.01


    IC LATCH-UP TEST

    • Historical Version

  3. JEDEC JESD78F


    IC LATCH-UP TEST

    • Historical Version

  4. JEDEC JESD78E

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    IC LATCH-UP TEST

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  5. JEDEC JESD78D


    IC LATCH-UP TEST

    • Historical Version

  6. JEDEC JESD 78C


    IC LATCH-UP TEST

    • Historical Version

  7. JEDEC JESD 78B


    IC LATCH-UP TEST

    • Historical Version