Language:
    • Available Formats
    • Options
    • Availability
    • Priced From ( in USD )
    • Printed Edition
    • Ships in 1-2 business days
    • $74.00
    • Add to Cart
    • Printed Edition + PDF
    • Immediate download
    • $100.00
    • Add to Cart

Customers Who Bought This Also Bought

 

About This Item

 

Full Description

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
 

Document History

  1. JEDEC JESD78E


    IC LATCH-UP TEST

    • Most Recent
  2. JEDEC JESD78D

    👀currently
    viewing


    IC LATCH-UP TEST

    • Historical Version
  3. JEDEC JESD 78C


    IC LATCH-UP TEST

    • Historical Version
  4. JEDEC JESD 78B


    IC LATCH-UP TEST

    • Historical Version