1820332

JEDEC JESD78D

IC LATCH-UP TEST

standard by JEDEC Solid State Technology Association , 11/01/2011

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Full Description

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
 

Product Details

Published:
11/01/2011
Number of Pages:
30
File Size:
1 file , 210 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus
 

Document History

  1. JEDEC JESD78F.02


    IC LATCH-UP TEST

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  2. JEDEC JESD78F.01


    IC LATCH-UP TEST

    • Historical Version

  3. JEDEC JESD78F


    IC LATCH-UP TEST

    • Historical Version

  4. JEDEC JESD78E


    IC LATCH-UP TEST

    • Historical Version

  5. JEDEC JESD78D

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    IC LATCH-UP TEST

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  6. JEDEC JESD 78C


    IC LATCH-UP TEST

    • Historical Version

  7. JEDEC JESD 78B


    IC LATCH-UP TEST

    • Historical Version