A METHODOLOGY IS PROPOSED FOR SCHEDULING SEMICONDUCTOR TEST OPERATIONS. WHILE CURRENT PRACTICE IN INDUSTRY IS BASED ON DISPATCHING RULES, OUR METHODOLOGY TAKES A MORE GLOBAL APPROACH. THE FACILITY OR JOB SHOP IS DECOMPOSED INTO A NUMBER OF WORKCENTERS. THE METHODOLOGY PROCEEDS BY SEQUENCING ONE WORKCENTER AT A TIME. A DISJUNCTIVE GRAPH REPRESENTATION OF THE FACILITY MODELS THE INTERACTIONS OF THE WORKCENTERS. ALGORITHMS MINIMIZE MAXIMUM LATENESS AND NUMBER OF TARDY JOBS ON TESTERS AND BATCH PROCESSING MACHINES. THE OVERALL METHODOLOGY HAS BEEN IMPLEMENTED ON A SET OF PROBLEMS BASED ON A REAL INDUSTRY SETTING.