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JEDEC JESD217.01

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

standard by JEDEC Solid State Technology Association , 10/01/2016

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Full Description

As ball grid array component pitch continues to decrease, the need to characterize solder voiding has become more significant. Solder void manifestation (type and/or sizes) has been used to determine process capability as a means of quality assurance during process transfer, and as indicators of process stability from in-line manufacturing monitors. This document describes how to characterize voids in solder spheres in ball grid array packages prior to surface-mount (SMT) reflow soldering.
 

Product Details

Published:
10/01/2016
Number of Pages:
46
File Size:
1 file , 1.7 MB
Note:
This product is unavailable in Russia, Ukraine, Belarus
 

Document History

  1. JEDEC JESD217A


    Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages

    • Most Recent

  2. JEDEC JESD217A


    Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages

    • Historical Version

  3. JEDEC JESD217.01

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    TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

    • Historical Version

  4. JEDEC JESD217


    TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

    • Historical Version