1775267

JEDEC JESD 24-2 (R2002)

ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD

Amendment by JEDEC Solid State Technology Association , 01/01/1991

This document is an amendment. View the base document.

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This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.
 

Product Details

Published:
01/01/1991
Number of Pages:
11
File Size:
1 file , 160 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus