2075034

JEDEC JESD8-33

.05 Low Voltage Swing Terminated Logic (LVSTL05)

standard by JEDEC Solid State Technology Association , 06/01/2019

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This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03
 

Product Details

Published:
06/01/2019
Number of Pages:
10
File Size:
1 file , 130 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus