Language:
    • Available Formats
    • Options
    • Availability
    • Priced From ( in USD )
    • Printed Edition
    • Ships in 1-2 business days
    • $67.00
    • Add to Cart
    • Printed Edition + PDF
    • Immediate download
    • $90.00
    • Add to Cart

Customers Who Bought This Also Bought

 

About This Item

 

Full Description

JEDEC JESD22-A117D is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.
 

Document History

  1. JEDEC JESD22-A117E


    ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

    • Most Recent
  2. JEDEC JESD22-A117D

    👀 currently
    viewing


    ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

    • Historical Version
  3. JEDEC JESD22-A117C


    ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

    • Historical Version
  4. JEDEC JESD 22-A117B


    ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

    • Historical Version