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Development of a standard simulation and related tool interface for component models written in VHDL, Verilog, C and other description languages.
To provide a standard method for interfacing and managing complex electronic models to design automation tools. This method is aimed at providing efficient, accurate, and tool independent tool interfaces suitable for large designs such as systems on a chip.
New IEEE Standard - Inactive-Withdrawn. The standard interface for hardware description models of electronic components is de-fined. The primary audiences of this standard are model developers and implementers of software supporting this interface.