IEEE 1076.1-2017
IEEE Standard VHDL Analog and Mixed-Signal Extensions
standard by IEEE, 01/26/2018
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About This Item
Full Description
Scope
This standard defines the IEEE 1076.1¿¿¿ language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS (VHSIC Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed
Integrated Circuits), the language is built on the IEEE 1076¿¿¿ (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.
Purpose
To support the design and verification of complex electronic systems containing a mixture of analog and digital devices, the IEEE 1076.1 language provides, as an extension of the IEEE VHDL 1076 language, a comprehensive set of capabilities for the description and simulation of mixed-signal and mixed-technology systems.
The revision adds selected new features to the language definition of IEEE Std 1076.1-2007, and it updates that standard to reflect changes in the VHDL specification, IEEE Std 1076-2008.
Abstract
Revision Standard - Active.
The IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems, is defined in this standard. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076-2008 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models. (Additional downloadable files are available for this standard at http://standards.ieee.org/downloads/1076/1076.1-2017/)
