THIS PAPER INVESTIGATES A COMPLEX ARCHITECTURAL APPROACH TO A LOW-LEVEL IMAGE SEGMENTATION ARCHITECTURE (LISA). OUR SEGMENTATION SCHEME CONSISTS OF A FEATURE EXTRACTION PART AND A DECISION ANALYSIS PART. THE ENTIRE ARCHITECTURE IS REALIZED ON TWO VME CARDS AND PERFORMS REAL TIME (20 MPIXELS/SEC) GREY LEVEL IMAGE SEGMENTATION BASED ON GREY LEVEL AND TEXTURAL PROPERTIES OF THE OBJECTS. WE ALSO INVESTIGATE TWO DIFFERENT TECHNOLOGY APPROACHES: FULL CUSTOM VLSI CMOS TECHNOLOGY AND PROGRAMMABLE GATE ARRAYS. WE SHOW HOW BOTH TECHNOLOGIES AND THE ASSOCIATED DESIGN METHODOLOGIES CAN BE USED ADVANTAGEOUSLY AT DIFFERENT PLACES IN A COMPLEX DESIGN.