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Full Description

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.
 

Document History

  1. JEDEC JESD235D

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    High Bandwidth Memory (HBM) DRAM (HBM1, HBM2)

    • Most Recent
  2. JEDEC JESD235C


    High Bandwidth Memory (HBM) Dram (HBM1, HBM2)

    • Historical Version
  3. JEDEC JESD235B


    HIgh Bandwidth Memory DRAM (HBM1, HBM2)

    • Historical Version
  4. JEDEC JESD235A


    HIgh Bandwidth Memory (HBM) DRAM

    • Historical Version
  5. JEDEC JESD235


    HIGH BANDWIDTH MEMORY (HBM) DRAM

    • Historical Version