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The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 128 bit data bus operating at double data rate (DDR).
 

Document History

  1. JEDEC JESD235B

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    HIgh Bandwidth Memory DRAM (HBM1, HBM2)

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  2. JEDEC JESD235A


    HIgh Bandwidth Memory (HBM) DRAM

    • Historical Version
  3. JEDEC JESD235


    HIGH BANDWIDTH MEMORY (HBM) DRAM

    • Historical Version