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This International Standard specifies the logical (relative timing and behavioral protocol) layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. This International Standard is intended to be used as a component within a profile (a collection of related specifications that must be used together by a product in order to claim conformance to a standard) to build systems with higher levels of compatibility. Futurebus+ provides the means for the transfer of binary information between boards over one or more logical buses. Boards may contain any combination of one or more processors and local resources such as cache, memory, peripheral and communication controllers, etc. Figure 1 shows a block diagram of a typical application of Futurebus+. Protocols are specified for the allocation of bus time to modules that need to conduct transactions with other modules over the bus. However, this International Standard does not mandate the priority rules for modules to use when competing for use of the bus. These are considered the privilege and responsibility of the system integrator. The International Standard includes a complete set of signaling rules to be followed by all modules in both the distributed and centralized control acquisition processes leading to bus mastership (clauses 4 and 5). The International Standard also gives a comprehensive set of signaling rules for all modules participating in a bus transaction (clause 6). Most of the transfer protocols in this International Standard are compelled; that is, they are governed by a pure cause-and-effect relationship. This is what gives this International Standard its technology-independent nature. The compelled signaling provides a designer with a logical simplicity for what takes place in the protocols. As a result, there will be maximum compatibility between products designed to this International Standard throughout its operational lifetime. With any bus, there is the dilemma of how much the standard should specify. There must be a balance between ensuring that all boards designed by a variety of manufacturers can operate together, while not restricting the users of the bus to any preconceived system design. Although the scope of this International Standard has been restricted to exclude many of the system requirements associated with bus-based computer systems, these are being addressed in companion standards.
New IEEE Standard - Active. This International Standard provides a set of tools with which to implement a Futurebus+ architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: a) a technology-independent, compelled-protocol, supporting broadcast, broad call, and transfer intervention (the minimum requirement for all Futurebus+ systems), and b) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance. Futurebus+ takes its name from its goal of being capable of the highest possible transfer rate consistent with the technology available at the time modules are designed, while ensuring compatibility with all modules designed to this standard both before and after. The plus sign (+) refers to the extensible nature of the specification, and the hooks provided to allow further evolution to meet unanticipated needs of specific application architectures. It is intended that this International Standard be used as a key component of an approved IEEE Futurebus+ profile.