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Full Description

Scope

The basic CAMAC specification (see Ref [1]) defines a single CAMAC operation as the activity which oc curs in response to a single CAMAC command. This activity may consist of the transfer of a single data word bet ween a CAMAC module and computer memory or the changing of the status of a module [for example, F (26), F (24)] or return of a value for Q as the result of a test made on the module, or any compatible set of the previously named activities. A block transfer is defined as a sequence of single CAMAC operations involving data which the user specifies by a command said to be of a higher level than one which specifies a single CAMAC operation. The higher level command contains all the information required for the specification of the desired sequence of single CAMAC command s and is interpreted by a channel which governs the activity on the CAMAC highway. Control information such as the readiness of the computer to participate in a data transfer, the state of the CAMAC Q line and the state of certain LAMs (Look-at-Me's) or special synchronizing signals must be made available to the channel. The use made of the control information by the channel defines the block-transfer mode. If a module is to influence the sequence of ope rations within a block transfer, then it must have the features required by the algorithm.

Abstract

New IEEE Standard - Inactive-Reserved. The recommended block-transfer algorithms are discussed, and those given in the basic CAMAC specification are described. These algorithms are well established and are supported by existing hardware. Some new algorithms are then discussed. Compatibility, hardware design, and software considerations are addressed.