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The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while enabling sufficient EDA application accuracy.
Revision Standard - Active. Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.