Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364(TM)-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800(TM)-2005.The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:-- The formal syntax and semantics of all Verilog HDL constructs-- The formal syntax and semantics of standard delay format (SDF) constructs-- Simulation system tasks and functions, such as text output display commands-- Compiler directives, such as text substitution macros and simulation time scaling-- The programming language interface (PLI) binding mechanism-- The formal syntax and semantics of the Verilog procedural interface (VPI)-- Informative usage examples-- Informative delay model for SDF-- The VPI header file
The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
Revision Standard - Superseded.
The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.