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Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.
To provide an industry standard based on the Verilog Hardware Description Language.
Revision Standard - Superseded. Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.