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Full Description

Scope

The standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain. The intent of this revision is to include a maximum subset of VHDL that can be used to describe synthesizable RTL logic. This includes considering new features introduced by IEEE Std 1076-1993, IEEE Std 1076-2002, new semantics based on algorithmic styles rather than template-driven, and a set of synthesis attributes that can be used to annotate an RTL description.

Purpose

The purpose of the standard is to define a syntax and semantics that can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use the IEEE 1076 standard. The original standard defined a syntax and semantics that was common amongst all synthesis tools at the time that it was created. The new standard expands the original purpose by including a maximal subset of VHDL that can be synthesized.

Abstract

Revision Standard - Inactive-Withdrawn. This document specifies a standard for use of very high-speed integrated circuit hardwaredescription language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructsare identified that should be ignored or flagged as errors.
 

Document History

  1. IEEE 1076.6-2004

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    IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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  2. IEEE 1076.6-1999


    IEEE Standard for VHDL Register Transfer Level Synthesis

    • Historical Version