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Full Description

Scope

This standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.

Purpose

The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications.

Abstract

Revision Standard - Inactive-Withdrawn. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.
 

Document History

  1. IEEE 1076-2008

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    IEEE Standard VHDL Language Reference Manual

    • Most Recent
  2. IEEE 1076-2002


    IEEE Standard VHDL Language Reference Manual

    • Historical Version
  3. IEEE 1076-2000


    IEEE Standard VHDL Language Reference Manual

    • Historical Version
  4. IEEE 1076-1993


    IEEE Standard VHDL Language Reference Manual

    • Historical Version
  5. IEEE 1076-1987


    IEEE Standard VHDL Language Reference Manual

    • Historical Version