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ESD TR18.0-02-20 outlines several EDA verification flows and tools used throughout the industry (Section 2.0) to uncover latch-up risks and how future EDA tool development could improve the latch-up verification flow. Section 3.0 gives an overview of scenarios beyond conventional latch-up, including grounded and biased n-wells, transient latch-up, native devices, radiation-induced latch-up, and special high voltage (HV) and FinFET technology requirements. Section 3.0 also includes a description of power management and system-level latch-up challenges, as well as a consideration of triggering parasitic structures during unpowered ESD events.