This standard practice establishes a test method for immunity scanning of ICs, modules and PCB's. Results from scanning relate to the system level performance but cannot be used to predict system level performance using the IEC 61000-4-2 test method. The reason is that variations exist in coupling paths between injection points and local current densities and associated fields coupled into traces or IC's.

This standard practice addresses testing of ICs, modules, and PCB's under powered conditions. This test method focuses on soft errors, such as bit errors and upsets, keeping in mind that fast pulses can also cause latch-up. Use of the standard practice will guide the user in the identification of the root causes of electrostatic discharge (ESD) induced soft errors in IC's, modules, and PCB;s, for debugging and quality control purposes.