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This standard defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages.
The purpose of this standard is to provide a well-defined language for formal specification of electronic system behavior, one that is compatible with multiple electronic system design languages, including IEEE Std 1076(TM) (VHDL(R)),1 IEEE Std 1364¿¿¿ (Verilog(R)), IEEE Std 1800¿¿¿ (SystemVerilog(R), and IEEE Std 1666(TM) (SystemC(R)), to facilitate a common specification and verification flow for multi-language and mixed-language designs. This standard creates an updated IEEE standard based upon IEEE Std 1850-2005. The updated standard will refine IEEE standard, addressing errata, minor technical issues, and proposed extensions specifically related to property reuse and improved simulation usability.
Revision Standard - Inactive-Reserved. The IEEE Property Specification Language (PSL) is defined in this standard. PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076¿¿¿ (VHDL¿¿), IEEE Std 1354 (Verilog¿¿), IEEE Std 1666¿¿¿ (SystemC¿¿), and IEEE Std 1800(TM) (SystemVerilog(R)), thereby enabling a common specification and verification flow for multi-language and mixed-language designs. PSL captures design intent in a form suitable for simulation, formal verification, formal analysis, and hybrid verification tools. PSL enhances communication among architects, designers, and verification engineers to increase productivity throughout the design and verification process. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.