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The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains: -- The formal syntax and semantics of all Verilog HDL construct; s -- Simulation system tasks and functions, such as text output display commands; -- Compiler directives, such as text substitution macros and simulation time scaling; -- The Programming Language Interface (PLI) binding mechanism; -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines; -- Informative usage examples; -- Listings of header A?les for PLI
New IEEE Standard - Superseded. The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.