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This standard defines a means of writing VHSIC hardware description language (VHDL) that guarantees the interoperability of VHDL descriptions among any register transfer level (RTL) synthesis tools that comply with this standard. Compliant synthesis tools may have features above those required by this standard. This standard defines how the semantics of VHDL shall be used; for example, to model level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability. The use of this standard should enhance the portability of VHDL designs across synthesis tools conforming to this standard. It should also minimize the potential for functional simulation mismatches between models both before and after they are synthesized.


To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use the current IEEE 1076 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their designs compliant with this developed standard.


New IEEE Standard - Superseded. A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.

Document History

  1. IEEE 1076.6-2004

    IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

    • Most Recent
  2. IEEE 1076.6-1999


    IEEE Standard for VHDL Register Transfer Level Synthesis

    • Historical Version