Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.