This standard defines a means of writing VHSIC hardware description language (VHDL) that guarantees the interoperability of VHDL descriptions among any register transfer level (RTL) synthesis tools that comply with this standard. Compliant synthesis tools may have features above those required by this standard. This standard defines how the semantics of VHDL shall be used; for example, to model level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability. The use of this standard should enhance the portability of VHDL designs across synthesis tools conforming to this standard. It should also minimize the potential for functional simulation mismatches between models both before and after they are synthesized.