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BS IEC 62530:2021

SystemVerilog. Unified Hardware Design, Specification, and Verification Language

standard by British Standard / International Electrotechnical Commission , 08/19/2021

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About This Item

 

Full Description

This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.

Cross References:
IEEE Std 1497-2001
ISO/IEC 9899:1999
IEEE Std 1364

All current amendments available at time of purchase are included with the purchase of this document.

 

Product Details

Published:
08/19/2021
ISBN(s):
9780539173413
Number of Pages:
1320
File Size:
1 file , 10 MB
Product Code(s):
30435564, 30435564, 30435564
 

Document History

  1. BS IEC 62530:2021

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    SystemVerilog. Unified Hardware Design, Specification, and Verification Language

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  2. BS IEC 62530:2011


    SystemVerilog. Unified hardware design, specification, and verification language

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  3. BS IEC 62530:2007


    Standard for SystemVerilog. Unified hardware design, specification and verification language

    • Historical Version